Tech Lead (Rust / Python) @ Lens
Jun 2025 – nowACE — post-layout verification for chip designs up to 300 GB
- Rewrote the DSPF/CDL ingestion pipeline from Python to Rust: 11,500 s → 35 s per GB.
- Rebuilt the render pipeline: ~3,500 s → 7.5 s per GB, with 100x+ less memory.
- Designed the DuckDB storage layer: typed schemas, hashed hierarchy indexing, safe edit flows.
- Set up CI for the Rust/PyO3 wheels with circuit regression tests. Mentor 4 engineers.